Abstract: First, the structure of a global positioning system (GPS) receiver and the RF downconverter MRFIC1502 produced by Motorola are introduced, and the hardware connection diagram for designing a GPS receiver with MRFIC1502 is given. Then, it analyzes the working principle of the receiver's RF input, IF filtering, phase-locked loop and sampling clock, and points out the issues that should be paid attention to in the design of printed circuit boards. introduction The space part of the global positioning system (GPS) uses a satellite constellation composed of 24 satellites with a height of approximately 20,200 km. The 21 + 3 satellites are all near circular orbits, with an operating period of about 11h58min (11:58), distributed on 6 orbital planes (4 per orbital plane), with an orbital inclination of 55 °. The distribution of satellites makes it possible to observe more than 4 satellites anywhere in the world at any time, and can maintain a geometric figure (DOP) with good positioning and calculation accuracy, providing continuous global guidance in time. Each satellite continuously broadcasts navigation information in two L-bands (390 to 1550 MHz). The two L-bands are link 1 (L1) with a frequency of 1574.42 MHz and link 2 (L2) with a frequency of 1227.6 MHz. The C / A code (Coarse AcquisTIon Code) and P code (Precise Code) are broadcast on L1, and the encrypted code (encrypted code) is only broadcast on L2. Motorola's RF down converter MRFIC1502 is designed to receive the C / A code on L1. This article mainly discusses the usage of MRFIC1502 as a down converter in GPS receivers. 1 Structure of GPS receiver The C / A code on L1 must be broadcast with a certain power gain to ensure that the minimum power on the user's receiving device is -160dBW (decibels). The 1575.42MHz carrier wave is modulated and contains C / A code and P code. In addition, the navigation data stream is transmitted through the carrier with a dual-phase shift key control method, and the data rate is 50 bps. The bandwidth of the C / A code is 2.046MHz (± 1.023MHz), and the bandwidth of the P code is 20.46MHz (± 10.23MHz). The GPS technical statement stipulates that when it is sunny, the power gain received by the receiver antenna is greater than -130dBW. Any obstacles, such as woods or buildings, will weaken the signal. Therefore, it is recommended that when considering the system sensitivity, leave at least a margin of 5.0-7.0dB for the system. The demodulation scheme will also affect the sensitivity of the entire receiver, and this must be fully considered when designing the system. Low noise amplifier is the most important part of GPS radio frequency receiver. This amplifier can basically determine the noise level of the entire receiver, so it is a direct determinant of receiver sensitivity. The low-noise amplifier is recommended to be implemented with MRFIC1501. When 5V power is supplied, the working current of MRFIC1501 is 7.0mA. For every 17dB increase in power, the noise signal increases by 1.5dB. The second filter is an ordinary filter, which must satisfy every 15dB increase in signal gain, and the noise increase cannot be greater than 3.0dB; the two ceramic filters are KFF6338, which is also a Motorola product. As the noise system increases by 1.0dB, the receiver sensitivity decreases by about 1.0dB, so when designing, the selection of filters and low-noise amplifiers should be fully considered. The choice of ceramic filter has a direct impact on the performance of the GPS receiver. If the selection is not good, the interference signal will be very large. The influence of the interference signal on the receiver has two aspects: first, if the out-of-band filtering is insufficient, the interference signal may cause the low-noise amplifier or down-converter to work nonlinearly, which may cause unreal output or increase the receiver Noise figure; second, if the interference signal of the demodulator is too large, the signal processed by the receiver is not real and cannot output positioning information. 2 Introduction to MRFIC1502 The module structure and pin arrangement of MRFIC1502 are shown in Figure 2. The chip is a quad flat package (TQFP) with a total of 48 pins. MRFIC1502 is a standard double down conversion, can be configured as a fixed frequency phase-locked loop (phase-locked loop) to generate two local oscillators and buffers, provide sampling clock for digital correlators and multiplexers. The active element used for L-band navigation oscillation is also synthesized in the film. The chip uses the silicon bipolar processing technology of Motorola's third-generation oxide self-aligned integrated circuits. The typical application circuit of the chip is given below. MRFIC1502 has a 50Ω resistor on the chip to match the RF input signal. The noise system of the input amplifier is about 4.5dB, and the gain is 13dB. The output of the amplifier is sent directly to the primary mixer. The mixer provides a conversion gain of 7.0dB, and its output is sent to the off-chip filter. The noise system of the input amplifier and mixer add up to 9.5dB. The amplifier and mixer are powered by independent VCC (42 pins) to reduce coupling with other circuits. This must be noted when designing external circuits and printing circuit boards. Generally, two bypass capacitors are connected to the 42 pin, one is used to filter the interference signal of high frequency components, and the other is used to filter the interference signal of low frequency components. These two capacitors should be as close as possible to the 42 pin to reduce the inductance of the line; similarly, the other ends of these two capacitors should be as close as possible to ground. In the design, if the above problems are noticed, the operation of the amplifier will be very stable; otherwise, the RF input may be very unstable. (2) One-stage IF filter The main function of the first-level IF filter is to filter the unwanted signals mixed in the mixing process of the mixer. The output impedance of the first-level mixer is 50Ω, and the input impedance of the first-level intermediate frequency amplifier is 1000Ω. The input impedance of the IF filter in this application is 50Ω, the output impedance is 200Ω, and its bandwidth is 15MHz. The output of the MRFIC1502 on-chip level converter is a TTL level signal, and the level problem should also be considered in the design. (3) Phase-locked loop design The signal of the voltage controlled oscillator (VCO) is 1527.68MHz, which is divided by 40 to obtain the dipole local oscillator frequency of 38.19MHz. In addition to providing the local oscillator signal for the second-level mixer, the second-level local oscillator signal outputs a 38 MHz signal through the converter as a sampling clock for the digital correlator and multiplexer. 38.19MHz is divided by 2 to obtain a frequency signal of 19.096. This signal is generally used for phase detection. The reference input (18-pin) of the phase detector is generally a minimum of 400mV and a maximum of 2.5mV. The phase detector of MRFIC1502 is designed based on MC12040, but some improvements have been made in terms of low consumption. (4) Sampling clock output The signal of the voltage-controlled oscillator is divided by 40, and then passes through the clock converter to change the sine wave into a TTL square wave. The TTL level signal is used as the sampling clock of the digital correlator and multiplexer. At the same time, it also provides an internal clock for other parts on the chip. Because the working frequency of the converter is 38MHz, and the output is a square wave, the waveform is relatively sharp. When the output end is connected in parallel with a 1000Ω resistor and a 40pF capacitor, the maximum instantaneous current may reach 50mA. Therefore, the converter is powered by a separate VCC pin (28 pin). In PCB layout, the bypass resistor should be as close as possible to the chip pins. Some important components can be arranged on the back of MRFIC1502, so that the path of MRFIC1502 to these components is as short as possible. The voltage-controlled oscillator may cause resonance with the impedance, and this must also be taken into consideration in the PCB layout. If the L-band input and the converter are too close together, current coupling may also occur. In applications, if this coupling occurs, the receiver becomes very sensitive to interfering signals. To reduce this coupling, a stripline structure can be used instead of a microwave transmission band structure. 4 Summary This article describes the method of using MRFIC1502 for GPS receiver design. The peripheral circuits given in this article are suitable for multiple different applications. For information on the MRFIC1502 chip, readers can log on to Motorola's website to get more and more widely used GPS receivers with the development of GPS. Due to the increasing integration of down-conversion chips provided by major companies, the design of GPS receivers should also become simpler. Mppt Solar Hybrid Inverter,Hybrid Solar Inverter With Mppt,Off Grid Hybrid Mppt Solar Inverter,Mppt Hybrid Solar Inverter With Batteries GuangZhou HanFong New Energy Technology Co. , Ltd. , https://www.zjgzinverter.com
Before the signal is sent to MRFIC1502, it is amplified and filtered twice. The various functional parts of the GPS receiver will be discussed below.
3 Implementation of GPS receiver
(1) RF input
(5) PCB layout rules