As we all know, the "black box" on the plane can record the flight status of the aircraft. Once the plane crashes, you can find the cause of the plane crash if you find the "black box". Similar devices can be used to record the running status of the car. This is what this article will study. That is to record the image status of the car. It can not only record the video images of the car driving in front of or around the car during the operation, but also Record video images in front of or around the car when it is stationary. Once there is a traffic accident or man-made damage to the car, etc., the video of the car condition recorded by the system can be used to analyze the situation at the time of the accident, and the cause of the traffic accident can be accurately determined, and the behavior of the car can also be Identification. This is of great significance for the identification of traffic accident liability, the analysis of accident causes, investigation and statistics, and the reduction of car theft and car destruction. Overall system design The hardware of the image monitoring system for automobile operation is mainly designed based on the ADSP-BF533 chip. The design is divided into CPLD circuit, image acquisition circuit, IDE interface circuit, SDRAM circuit, FLASH circuit, power supply circuit and reset circuit. The overall block diagram of the system is shown in Figure 1. Figure 1 overall block diagram of the system 1 Introduction of ADSP-BF533 ADSP-BF533 is a powerful DSP recently introduced by the ADIBlackfin series. 2 MPEG-4 compression algorithm The MPEG-4 standard uses object-oriented video coding technology. According to the object-oriented coding requirements, MPEG-4 introduced the concept of video object (VO). The video object is an abstract description of the scene in the visual scene. From the perspective of the user, it represents any meaningful physical entity in the picture, such as people, objects or even the background. MPEG-4 is a dynamic image standard that enables you to change from passive to active (no longer just watching, allowing you to join, that is, interactive). Hardware system design 1 Memory circuit design The system memory includes data memory and instruction memory, and its memory circuit is composed of SDRAM and ADSP-BF533 interface circuit, Flash and ADSP-BF533 interface circuit. This system SDRAM adopts HY57V561620 of Hynix Company. The interface between SDRAM and ADSP-BF533 is shown in Figure 2. Figure 2 SDRAM and ADSP-BF533 interface circuit HY57V561620 is a high-speed synchronous dynamic memory. Since all its addressing, refreshing and other operations are completed by the control system integrated inside the chip, it is very simple to use. The storage space of HY57V561620 is 32Mb, which is more than enough for ordinary video applications, and it speeds up the access speed, so it can be widely used in multimedia systems, video capture and editing systems, etc. This system uses 2 AM29LV800BT, its BYTE # is 8-bit or 16-bit select mode pin, the system uses 16-bit data mode, so this pin is connected to high level; the reset pin RESET # is connected to CPLD. The interface diagram of AM29LV800BT and ADSP-BF533 is shown in Figure 3. Figure 3 AM29LV800BT and ADSP-BF533 interface circuit AM29LV800BT is 1Mb, operating voltage is 2.7 ~ 3.6V, can be configured to 8-bit or 16-bit data width. It has 19 sectors in total and can work with 8-bit (byte mode) or 16-bit (word mode) data width. Because AM29LV800BT has a booster circuit inside, it only needs a 3.0V power supply to complete the programming and erasing operations in the system. By writing a command sequence that complies with the JEDEC standard to its internal command register, the Flash can be programmed (programmed), erased in whole, erased by sector, and other operations.
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A large number of images, sounds, texts, and data streams used in the Internet are suitable for telecommunications and various Internet devices. The ADSP-BF533 core includes 2 16-bit multipliers, 2 40-bit accumulators, 2 40-bit arithmetic logic units (ALU), 4 8-bit video ALUs, and 1 40-bit shifter. 
