The digital signal microprocessor DSP has the functions of high-speed operation and data processing. With its advantages of high performance and low power consumption, it provides an effective hardware platform for the mathematical calculation of the real-time navigation system. In modern weapons and equipment, a car navigation system based on DSP chips is designed, which plays an important role in both the civil and military fields. The system has the characteristics of high reliability and safety. 1 Working principle of car navigation system The main function of the car navigation system is to collect the gyro quadrature encoding signal, accelerometer input and odometer input signal regularly, and perform necessary processing on the collected data to realize navigation solution. At the same time, the collected data is sent to the ground monitoring equipment through the RS422 bus and the CAN bus; and the relevant commands and parameters are received through the RS422 bus. The system structure is shown in Figure 1. Figure 1 Block diagram of the car navigation system 2 System hardware design 2.1 Processor and memory design The car navigation system circuit uses TI’s TMS320C6713B-A200 as the DSP. The DSP chip has a nominal main frequency of 200 MHz, and the DSP processing capacity is 1600 MI·s-1/1 200MFLOPS when working at a main frequency of 160 MHz. Use a 40 MHz crystal oscillator as the clock input of the DSP, which is used as the clock for the DSP after being multiplied by the internal phase-locked loop. A piece of TPS70345 voltage regulator is used to provide it with a 3.3 V IO voltage and a 1.2 V core voltage; a piece of capacity is used The 16 MB MT48LC4M3282TG-7IT chip is used as the SDRAM memory. The memory is directly connected to the EMIF bus of the DSP. The address lines BA1, BA0 and A11～A0 of the SDRAM chip are connected to the EA15～EA2 of the DSP chip, and the data lines D31～D0 are connected to ED31～ ED0. The address lines A22～A0 of the FlashRom chip are connected to GP13～CP11 and EA21～EA2 of the DSP chip, and the data lines DQ15～DQ0 are connected to ED15～ED0. The state of the GP13～GP13 pins is high during initialization, and the chip select signal of the SDRAM chip Connect to CE0 of DSP chip; adopt a S29GL128N10TFIR1 chip with a capacity of 16 MB as FlashRom memory, and connect the chip selection signal of FlashRom chip to CE1 of DSP chip. The reason why the CE1 of the DSP chip is connected to the FlashRom chip selection is that its boot mode is loaded from ROM, and the BOOT program is stored in the FlashRom memory. The read and write signals of the memory are all connected to the AWE signal of the DSP chip. The DSP accesses the external memory through the EMIF bus interface, and can control the access to the external memory through the operating register, which simplifies the design of the circuit. 2.2 Power supply design The input power of the car navigation system is 27±9 V. The 24 V is converted into voltages of +15 V and +5 V by MHF+28515. The input voltage range of MHF+28515 is 16～48 V, and the output power is 15 W. The maximum output power of 5 V voltage is 7.5 W, the current is 1 500 mA, and the maximum output power of +15 V voltage is 5 W, and the circuit is 330 mA. Since the current used by the +5 V power supply of the car navigation system circuit itself is about 1000 mA, it can provide +5 V with a current> 140 mA output for external use. In order to meet the power supply requirements of various components in the system, the car navigation system is designed power supply system. The +5 V power supply output by MHF+28515 provides digital power for the entire module, among which some +5 V working chips such as CAN bus protocol chip directly use this power; other circuits use the converted power supply. The processing methods include: voltage adjustment The TPS70345 converts the +5 V power supply into 3.3 V and 1.2 V power supplies. Among them, 3.3 V is used by DSP peripheral circuits and SDRAM, Flash and other chips, and 1.2 V is used by the DSP core. The +5 V power supply is converted into 3.3 V and 1.8 V voltage, of which 3.3 V is used by FPGA peripheral circuits, optocouplers and other chips, and 1.8 V is used by FPGA core; the +5 V power supply is converted into 3.3 V voltage through two DC/DC modules NKE0503, one for RS422 The MAX3490 and optocoupler in the isolation circuit are used, and the other is for the MAX3232 and optocoupler in the RS232 isolation circuit. The +5 V power supply is isolated by a DC/DC module NME0505 for MAX481, CAN bus transceiver and optocouplers on its path. The ±15 V power output from MHF+28515 provides analog power for the entire module. The +15 V voltage is converted into +5 V analog voltage through the three-terminal regulator JW78M05 for use by LM3940IMP and REF196; +5 V analog voltage passes LM3940IMP converts into 3.3 V analog voltage to power the op amp; +5 V analog voltage is converted to 3.3 V analog voltage through REF196 to power the bridge; +15 V and -15 V are to power the op amp OP497. 2.3 Input signal The input signal of the car navigation system circuit includes 3 accelerometer signals, 3 gyro signals, 2 odometer signals, 2 standard frequency signals, 1 driving status signal, 9 status detection signals and 10 temperature measurement signals. The signal form of the accelerometer signal is reversible pulse, amplitude TTL, full scale is 256 kHz, counted by 3 16-bit counters, rising edge trigger, interrupt 5 latch, accelerometer signal adopts RC filter and Schmitt trigger input Inverter of â€is reshaped, and then introduced into FPGA after level conversion by 74LVC244. The signal form of the gyro signal is a quadrature coded signal, the amplitude is high level 4～5 V, low level 0～0.8 V, current ≤8 mA, frequency ≤1.5 MHz, phase difference 90°±20°, through 3 channels The 16-bit counter counts, the rising edge is triggered, and the interrupt 5 is latched. The gyro signal is also the same as the accelerometer signal and undergoes shaping. The frequency of the standard signal is 128 kHz, the amplitude is TTL, and the signal needs to be shaped. Therefore, the processing form of the standard frequency signal is the same as that of the accelerometer signal. The odometer signal includes two odometer signals, one driving status signal and one odometer ground. The amplitude is 12 V and the driving capacity is 30 mA. Optocoupler isolation is required. Two 16-bit counters and a 1-bit status register are set up, respectively. Record the pulse input and status information of the odometer, the rising edge of the odometer pulse triggers the counting, and the interrupt 5 is latched; the driving state signal State can be enabled and disabled by commands. When State=1 in the enabled state, the odometer signal counts up; When State=0, the counting is subtracted; when the odometer signal is added and counting in the prohibited state, the odometer signal passes through the RC filter circuit and the protection diode, and then enters the FPGA through the light barrier. The state detection signal includes 3 mode hopping detection signals, 3 high-voltage state signals, and 3 machine-jitter state signals. The signal forms are all on-off signals with an amplitude of TTL. The machine-jitter state signals and high-voltage state signals need to be isolated by optocouplers. The mode hopping detection signal processing form and parameter selection are the same as the accelerometer signal; the high-voltage state signal and the machine jitter detection signal processing form are the same as the gyro signal. The temperature measurement signal includes 10 channels of temperature measuring resistor input and 1 channel of temperature measuring resistor input common terminal, the temperature range is -45～+70℃, the temperature measuring resistor and 3 high-precision resistors on the module form an electric bridge, according to the working principle of the bridge , The resistance of the bridge arm resistance should be less than the minimum value of the temperature measuring resistance, and some redundancy should be considered. The calculation formula of the temperature coefficient is R0×3.85×10-3, where R0 is a 0℃ resistance, due to the high precision Resistance and 12-bit AD, A/D conversion accuracy> 0.5 ℃, can be realized by multiple switches. The midpoints of the two arms of the bridge are respectively connected to the operational amplifier for follow-up processing, and then after the post-amplification, the A/D conversion chip collects the temperature test results. The A/D conversion chip uses a serial interface chip and is connected to the McBSP1 interface of the DSP. The chip has a resolution of 12 bits, and has a conversion time of 10 μs and a maximum of 11 A/D inputs. The CAN bus design is adopted in the circuit design of the car navigation system. CAN bus independent controller adopts SJA1000T, using 16 MHz crystal oscillator as clock input, ID number and data transmission baud rate can be configured through software, the maximum rate is 1 Mbit·s-1. Its bus controller uses a data address multiplexing bus, which is connected to the DSPEMIF bus after being converted by FPGA. CAN bus controller signal adopts TTL level (5 V), and SN74LVC4245 is used for level conversion between FPGA with signal of 3.3 V level. The CAN bus receiver uses Philips Semiconductors PCA82C250. The data transmission signal between the bus controller and the transceiver is isolated by an optocoupler. CAN bus interface circuit is shown as in Fig. 2. Figure 2 CAN bus interface circuit 2.4 FPGA design The car navigation system circuit adopts the control logic on the FPGA processing module, the counting of each input signal and the realization of the serial interface communication protocol. FPGA counts the input signal, and divides the frequency of the standard frequency signal to generate an interrupt 5 signal. When the interrupt 5 signal is generated, each counter value is latched. The DSP can access the internal resources of the FPGA through the EMIF bus, and the address space occupies CE2 of the EMIF bus. The loading mode of FPGA is Master Serial Mode, and the functional block diagram of FPGA is shown in Figure 3. FPGA design includes accelerometer signal counter design, gyroscope signal counter design, odometer signal counter design, gyroscope frequency counter design, standard frequency divider design, status detection, fault detection signal and serial communication interface design. Figure 3 FPGA functional block diagram The accelerometer signal input is a reversible pulse. Each channel accelerometer input includes 3 signals, which are +A, -A and GND. According to the design requirements, the count value increases when there is a pulse on the +A signal, and there is a pulse on the -A signal When the time count value is reduced, when the frequency standard frequency division interrupt is generated, the count result is stored in the latch. A 16-bit counter is designed in FPGA. The power-on reset counter is 0. When there is a pulse on the +A signal, the count value is increased by 1, and when there is a pulse on the -A signal, the count value is subtracted by 1. Store the counting result in the latch, and the DSP can access the latch through EMIF to get the result of the accelerometer signal counter. The gyro signal input form is a quadrature coded signal. Each channel gyro signal input includes 3 signals, namely A, B and DGND. When the A phase leads the B phase by 90°, the count value increases, and when the A phase lags the B phase by 90° When the count value decreases. In the design, the input signal first passes through the phase detection circuit to identify the phase sequence of the A signal and the B signal, and generate two reversible pulse signals of 4 times the frequency, and then count the reversible pulses. When the standard frequency signal is interrupted, the The counting result is stored in the latch. The odometer signal includes two counting inputs and one driving state signal input. Each counting input uses a 16-bit counter. When an interrupt occurs, the counter value is stored in the latch; the driving state signal (STATE) is initially in an invalid state after power-on , The user sets whether the STATE state is valid through commands. When the STATE signal is in a valid state, STATE is 1, and the odometer counter counts up; if STATE is 0, the odometer counter counts down; and when the STATE signal is in an invalid state, the odometer counter counts up. A 16-bit counter is designed in FPGA, the power-on reset counter is 0, the value of the counter is increased, and the counter is increased by 1, when the frequency scale division interrupt is generated, the counting result is stored in the latch. DSP can access the latch through the EMIF to get the result of the gyro frequency counter. The standard frequency divider is used to divide the frequency of the standard frequency signal to generate a state interrupt signal that latches the count value of the accelerometer, gyro counter, and odometer counter in the FPGA and the state detection signal. The standard frequency divider in FPGA consists of a prescaler and a counter. The frequency division can be programmed by software. The DSP writes the value to be divided into the prescaler through the EMIF bus. The counter records the number of frequency standard pulses and counts. When the calibration value is reached, the counter outputs and clears, and the counter outputs an interrupt to the DSP, and at the same time latches the count value of the accelerometer, gyro counter, and odometer counter in the FPGA and the status of the status detection signal. The status detection signal is a switch signal, and the status is stored in an address, and each bit represents the status of one channel. A 16-bit register is designed in FPGA to store driving status, high voltage detection signal status, machine shake detection signal status, and mode jump detection signal status, and the signal is latched in the latch when interrupted. The fault detection signal is written into the fault detection vector through an address. According to the specific value of each bit of the fault detection vector as 0 or 1, the programmable logic device automatically sets the output pin of the fault detection vector. Set up an 8-bit memory in the FPGA to store the fault detection vector, and the signal is output after being driven. A serial protocol module is designed inside FPGA, which forms RS232 and RS422 serial interfaces through external circuits. The integrated protocol chip is designed with reference to ST16C2552, and its MODEM control functions have been cut. The working baud rate of the serial interface can also be set. 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So what is a wireless router?
Wireless router, according to the definition of Baidu Encyclopedia: Wireless router is used for users to access the Internet, with wireless coverage of the router.
A wireless router can be thought of as a repeater that forwards the broadband network signal from the wall of your home through an antenna to nearby wireless network devices (laptops, Wifi-enabled phones, tablets, and all Wifi-enabled devices).
The popular wireless routers in the market generally support four access methods: dedicated xdsl/cable, dynamic xdsl, pptp, and generally can only support 15 to 20 devices online at the same time. It also has some other network management functions, such as dhcp service, nat firewall, mac address filtering, dynamic domain name and so on. The signal range of the general wireless router is 50 meters radius, and the signal range of some wireless routers has reached 300 meters radius.
The name of wireless router can be separated out of two keywords: wireless and routing.
Understand the technical principle behind these two words, you understand the wireless router.
Wireless is also what we often call Wi-Fi. Wireless routers can convert home broadband from wired to wireless signals, and all devices can happily surf the Internet as long as they connect to their own Wi-Fi. In addition, these devices also form a wireless local area network, where local data is exchanged at high speed and is not limited by the bandwidth of home broadband.
For example, many people have smart speakers in their homes that can be used to control various smart appliances. When you say small X small X, turn on the TV, the speaker actually finds the TV through the LAN and sends instructions, and does not need to connect to the Internet; And if you let it broadcast news, you have to get data through the Internet.
The Local Area Network we talked about earlier, also known as the Intranet, is represented by the Local Area Network (LAN) on the router, so the Wi-Fi signal is also called WLAN(Wireless LAN); The Internet we want to access, also known as the extranet, is represented on the router by the WAN(Wide Area Network).
On the Intranet, the IP address of each device is different, which is called a private address. All devices on the Internet share the same public address, which is assigned by broadband operators such as China Telecom Unicom.
The router is the bridge between the Intranet and the external network. The above mentioned IP address translation, packet forwarding, is the router routing function. In other words, the router is the hub of the home network, and the data of all the devices must be forwarded through it to access each other or reach the external network, which means that one husband is the key and ten thousand men are not open, so the comprehensive router is also called "home gateway".
Second, the demand for wireless routers
I do not know if there is a sudden WIFI break when you play games at home, and a stable router is crucial at this time. However, it is important to note that your WIFI frequently dropped may not be a problem with the router, it may also be a problem with the carrier network. (Router means I don't back this pot)
In fact, for most people, there are two basic requirements for wireless routers
Stable and do not drop
Fast Internet and easy setup
Some people will have some advanced needs:
There are some features, USB interface, can be external U disk or hard disk, can achieve simple nas functions, QOS, etc., to advertising and so on
Mesh networking, when the house area is large, multiple routers can be used for Mesh networking
How to choose a wireless router
The wireless router market is in the transition stage from WiFi 5 to WiFi 6, if you want to buy the first choice is definitely WiFi 6 wireless router, which is the future trend.
The speed of WiFi 6 is nearly 40% higher than the previous generation 802.11ac, and the highest connection speed can even reach 9.6Gbps, while the highest speed of 802.11ac is only 6.93Gbp. More importantly, unlike 802.11ac, which only covers the 5GHz band, WiFi 6 covers 2.4GHz and 5GHz. Although the 5GHz band has less interference, it has weak wall penetration ability, and the 2.4GHz band has strong wall penetration ability, which takes into account each other.
So why choose a WIFI6 router?
Compared with the previous generation of 802.11ac WiFi 5, the maximum transmission rate of WiFi 6 in the 5Ghz band has been increased from 3.5Gbps to 9.6Gbps, and the theoretical speed has been increased by nearly 3 times. WiFi 6's 5Ghz single-stream 80Mhz bandwidth can reach theoretical speeds of up to 1201Mbps and 160Mhz bandwidth of up to 2402Mbps.
The band supports 2.4Ghz and 5Ghz.
In terms of modulation mode, WiFi6 supports 1024-QAM, which is higher than the 256-QAM of WiFi 5, and the data capacity is higher. Some high-end WiFi 6 routers support 4096-QAM.
WiFi6 supports MU-MIMO (multi-user multiple-input multiple-output) technology, and supports both upstream and downstream MU-MIMO, with a maximum support of 8T×8R MU-MIMO. The speed is greatly improved. High concurrency, WiFi6 5GHz band, terminal connections up to 128! 5 times that of WiFi5. Effectively solve the Internet needs of multi-person networking and smart home;
WiFi6 adopts OFDMA (orthogonal frequency division multiple access) technology. After using OFDM to parent the channel, the transmission technology of transmitting data is loaded on the subcarrier, allowing different users to share the same channel, allowing more devices to access, with shorter response time and lower delay.
Low latency, WiFi6 time delay can be as low as 10ms, compared to WiFi5 30ms delay, only 1/3. This performance refresh is extremely friendly to game lovers;
If WiFi6 (wireless router) devices need to be certified by the WiFi Alliance, they must use the WPA 3 security protocol, which is more secure.
The WiFi6 wireless router is backward compatible with WiFi5 and WiFi4 terminals.
Fourth, the misunderstanding of purchasing routers
Is the through-wall router really through-wall?
Mistake; The country has strict limits on the transmission power of the wireless router antenna, if you have a lot of rooms in your home, and there are many walls between them, even if you buy an expensive wireless router, you can not do one to cover all the room signals. If the signal is not good, you can consider multiple wireless router Mesh networking.
Does a wireless router have a stronger signal with more antennas?
More antennas just to match the X*X MIMO mode, the more antennas, the more channels, can only ensure that the network is more stable, the impact on the signal is little, the strength of the signal is only related to the wireless transmission power. The wireless transmission power of the country has a standard.