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MPEG (Moving Picture Professionals) was established in 1988 to determine a single encoding and decoding (compression/decompression) method for digital audio. In 1992, the International Organization for Standardization (ISO) and the International Electrotechnical Commission (IEC) established the MPEG1 (ISO/IEC11172) standard for audio and video coding. This allows the industry to unify all types of audio/video media emerging in the new digital century in a single format.
With the development of the MPEG Audio Layer 3 (MP3) format for storing and playing music in digital form, the personal digital player market is beginning to show tremendous growth opportunities. An uncompressed audio track has an MP3 digital file that is only 1/10 the original track size. A 650 Mbytes read/write CD capable of maintaining a 74-minute digital audio recording time can maintain 740 minutes of MP3 compressed audio data.
The general solution for digital players is in the form of software (such as "Internet Audio Player" based on Windows or other OS) or hardware (such as "Portable MP3 Player"). For example, Diamond Multimedia's Rio PMP300 and Rio PMP500 MP3 digital players use Actel's A40MX04 and A40MX09 FPGAs to achieve their specific application functions. FPGAs can meet the price, power, and performance requirements of the entire system. The A40MX04 provides 547 logic blocks that can be configured as combinatorial logic or 273 flip-flops and 69 I/Os that implement interface logic. The A40MX04 and A40MX09 easily meet the 48MHz speed requirement. Their flexible architecture allows system designers to optimally implement a variety of functions in each MP3 player.
MP3 digital player system requirements
The MP3 player has two basic modes of operation: download mode and play mode. In the download mode, the software running on the PC allows the user to download the MP3 file to the flash card in the player. Once all the files have been downloaded, the player is disconnected from the PC and the downloaded music is listened to through the headphones. MP3 players have different playback selection controls such as play, fast forward, fast reverse, stop/pause, volume control, random play and repeat play.
The MP3 player contains software that can be input to the PC. The software provides a user interface to select, sequence and download MP3 files of different music to the player via the PC parallel port. Figure 1 shows a system level block diagram.
Download music to the player via the parallel port at a rate of approximately 10 seconds per 1MB of encoded music. The small size of the MP3 player has strict limits on the physical dimensions of all components. In addition, the MP3 player is a portable, battery-powered device that needs to operate at low power of approximately 180mW. These two factors have a great influence on the component selection of the functional design.
Implementing MP3 System with FPGA
Figure 2 shows the block diagram of the Rio PMP500 system. The A42MX09 FPGA acts as an interface FPGA. It includes a CPU interface, flash and smart memory interfaces with ECC (Error Correcting Code) support, clock generation logic, function control logic, and key function detection logic. .
The CPU I/F unit in the A42MX09 provides a communication path to the system CPU (NECD78P064GC microcontroller with integrated LCD controller). The CPU runs at 2.5MHz and controls the operation of the entire system. For any desired operation, the CPU wakes up the system and sets up the entire system. The CPU accesses system memory and manages the configuration, programming, and access of the entire flash. The CPU has an interface to the MP3 processor. The data read by MP3 from the flash memory is written by the CPU to the MP3 processor. The MP3 processor decodes the MP3 data and sends the data to the DAC for analog output to the headphones.
The smart memory interface unit in the A42MX09 is the interface to the smart memory card. A smart memory card is an external flash memory that is used to add the entire system memory to store more songs in the player. The signal interface to the smart memory card is very similar to the flash interface.
The flash interface unit is used to control the flash memory, and the flash memory saves the MP3 file downloaded through the parallel port. In addition, ECC is implemented using the Hamming code function. The Hamming code is an FEC (Forward Error Correction) tool that corrects errors when the data used passes through the noisy media. The raw data has additional check bits appended to each block to generate a codeword. These extra bits are calculated using the "Block Parity" mechanism. The matrix G is generated using the data bits of the modulo 2 operation to obtain a Hamming codeword. This requires a multiplication function, and the multiplication function is easily implemented using the combination of logic modules in the A42MX09.
The clock generator in the A42MX09 generates different clocks required to drive different logic cells inside the device from the 48MHz input clock. The clock generation logic unit is composed of a flip-flop and a combinational logic to form a frequency divider. The keyboard detection unit in the A42MX09 is used to change the settings of the player. The keyboard interface unit is generally constructed of a logic unit that detects a connection point (according to a button) in the keyboard array and converts the button into a function associated with the key. Perform appropriate functions based on button detection. The array is implemented by registers, latches, and combinatorial logic.
The power of the Rio MP3 player is controlled by the MAX1M1705 device, while the 1705 is controlled by the FPGA power control unit. MP3 players are typically powered by a single 1.5V battery. The battery should last for at least 12 hours to listen to all downloaded music. Power control is a notable feature of the Rio MP3 player. Power control devices have two power modes of operation: PFM (Pulse Frequency Modulation) and PWM (Pulse Width Modulation) modes.
PFM mode is a low quiescent current standby mode that provides 120mA total output current and reduces static power consumption to 500uW. The PWM mode is a high power mode that provides up to 450mA of output current. When the MP3 player is in the stop state, the CPU program writes a register of the FPGA, thereby generating a MODE signal to place the MAX1M device into the PFM low power mode. In the PFM mode, the Rio MP3 player consumes only 2mW to 3mW. When the MP3 player is operating, the MODE signal changes the MAX1M device to PWM mode. The total power of the Rio MP3 player when working is about 180mW.
Next generation MP3 system
The next-generation MP3 system will change the current system, providing faster downloads, more music files for playback, and more users to choose from interface/keyboards. Faster downloads can be achieved by using high-speed parallel port mode (see IEEE1284) or USB port. The use of high-density flash memory along with a local SDRAM-based song cache provides more music file playback and offers additional options such as fast play, fast forward, slow play, program play, and more. Other options may include an infrared transceiver that allows the user to transmit data back and forth from the player to the player or perform some remote control operations. The entire system can be implemented in one FPGA and does not require a CPU. The audio DAC controller logic unit in the FPGA provides an I2C interface to control the audio DAC. The audio DAC takes serial audio data through the I2C interface and converts it to analog audio for the headset.
Other new compression methods are emerging, with the ATRAC3 (Adaptive Transform Acoustic Coding) standard compressing CD music data by 10:1 while maintaining CD quality. The ATRAC3 features are:
1. Obtained by signal analysis by band splitting filter and MDCT (Modified Discrete Cosine Transforms).
2. Bit rate compression. With ATRAC3 technology, high-efficiency compression of music signals can be achieved. 
