FPGA is a programmable chip, so the design method of FPGA includes hardware design and software design. The hardware includes FPGA chip circuits, memory, input and output interface circuits, and other devices. The software is the corresponding HDL program and the latest popular embedded C program. At present, microelectronics technology has developed into the SOC stage, that is, the integrated system stage, which has revolutionized the design idea of ​​integrated circuits (ICs). SOC is a complex system that integrates the functions of a complete product on a single chip, including core processor, storage unit, hardware acceleration unit, and numerous external device interfaces. It has a long design cycle and high implementation cost. The design method must be the top-down software and hardware collaborative design from the system level to the functional module, achieving a seamless combination of software and hardware. Such a large workload is clearly beyond the capabilities of a single engineer, so it needs to be implemented in a hierarchical, structured design approach. First, the chief designer divides the entire software development task into several operational modules, evaluates its interfaces and resources, compiles the corresponding behavior or structural model, and assigns it to the next layer of designers. This allows multiple designers to simultaneously design different modules in a hardware system and is responsible for the modules they design; then the upper layer designers perform functional verification on the lower modules. The top-down design process starts with a system-level design, divides it into several secondary units, and then divides each secondary unit into the basic unit of the next level, and continues until it can be directly implemented using basic modules or IP cores. So far, popular FPGA development tools provide hierarchical management, which can effectively sort out intricate layers and easily view the source code of a certain level of modules to modify errors. In engineering practice, there is also the problem of software compilation time. Because large-scale design contains multiple complex functional modules, its timing closure and simulation verification complexity is very high. In order to meet the requirements of timing indicators, it is often necessary to repeatedly modify the source files, and then recompile the modified new version until the requirements are met. until. There are two problems in this: First, the software can take up to several hours or even weeks to compile, which is not tolerated by development; secondly, the results after recompilation and place and route are very different, and the timing will be satisfied. The circuit is broken. Therefore, it is necessary to propose a software tool that effectively improves design performance, inherits existing results, and facilitates team-based design. FPGA vendors are aware of this type of need and have developed software tools for logical locking and incremental design. For example, Xilinx's solution is PlanAhead. Planahead allows high-level designers to partition the corresponding FPGA chip area for different modules, and allows the underlying designer to independently design, implement, and optimize in a given area, and then integrate the design after each module is correct. If an error occurs in the design integration, it can be modified separately without affecting other modules. Planahead combines structured design methods, team-based collaborative design methods, and reused inheritance design methods to effectively improve design efficiency and design cycle. However, it can be seen from the description that the new design method has high requirements for the top designer of the system. In the early stage of design, they not only need to evaluate the resources consumed by each sub-module, but also need to give corresponding timing relationships; in the later stage of design, the corresponding revisions need to be completed according to the implementation of the underlying modules. The FPGA design flow is the process of developing FPGA chips using EDA development software and programming tools. The development process of a typical FPGA is generally shown in Figure 4.1.1, including function definition/device selection, design input, function simulation, comprehensive optimization, post-synthesis simulation, implementation, post-route simulation, board-level simulation, and chip programming and debugging. The main steps. Before the start of the FPGA design project, there must be a definition of the system function and the division of the module. In addition, according to the task requirements, such as the function and complexity of the system, the work speed and the resources, cost, and connection of the device itself can be laid. Weigh the sex and other aspects, choose the right design and the right device type. Generally, the top-down design method is adopted, the system is divided into several basic units, and then each basic unit is divided into the basic units of the next level, and this is continued until the EDA component library can be directly used. Design input is the process by which the designed system or circuit is presented in some form of development software requirements and entered into the EDA tool. Commonly used methods are hardware description language (HDL) and schematic input methods. The schematic input method is one of the most direct description methods. It is widely used in the early development of programmable chips. It will transfer the required devices from the component library and draw the schematic diagram. Although intuitive and easy to simulate, this method is inefficient and difficult to maintain, which is not conducive to module construction and reuse. The main disadvantage is that the portability is poor. When the chip is upgraded, all the schematics need to be modified. At present, the most widely used in practical development is the HDL language input method, which can be divided into ordinary HDL and behavioral HDL by text description design. Ordinary HDL has ABEL, CUR, etc. It supports expressions such as logic equations, truth tables, and state machines, and is mainly used for simple small designs. In medium and large projects, the behavioral HDL is mainly used, and the mainstream languages ​​are Verilog HDL and VHDL. Both languages ​​are standards of the Institute of Electrical and Electronics Engineers (IEEE). Their common features are: language is independent of chip technology, it is conducive to top-down design, easy to partition and transplant modules, portability is good, It has strong logic description and simulation functions, and the input efficiency is very high. In addition to this IEEE standard language, there is also the vendor's own language. It is also possible to use HDL as the main method and the schematic diagram as a supplementary hybrid design method to play their respective characteristics. Functional simulation, also known as pre-simulation, performs a logical function verification of the circuit designed by the user before compiling. At this time, the simulation has no delay information and only the preliminary function is detected. Before the simulation, the waveform file and the test vector (that is, the input signals of interest will be combined into a sequence) by using the waveform editor and HDL. The simulation result will generate the report file and the output signal waveform, from which the signal of each node can be observed. Variety. If an error is found, return to the design modification logic design. Commonly used tools are Model Tech's ModelSim, Sysnopsys' VCS, Cadence's NC-Verilog, and NC-VHDL. The so-called synthesis is to transform the description of the higher level abstraction into a lower level description. The integrated optimization optimizes the generated logical connections according to the target and requirements, and planarizes the hierarchical design for FPGA layout software. At the current level, Synthesis refers to compiling design inputs into logically connected netlists composed of basic logic elements such as AND gates, OR gates, NOT gates, RAMs, and flip-flops, rather than real gate-levels. Circuit. Real and specific gate-level circuits need to be generated by the FPGA manufacturer's place-and-route function based on the synthesized standard gate-level structure netlist. In order to be converted into a standard gate-level netlist, the HDL program must be written to match the style required by a particular synthesizer. Since the integration of gate-level structure and RTL-level HDL programs is a mature technology, all synthesizers can support this level of synthesis. Commonly used synthesis tools are Synplicity's Synplify/Synplify Pro software and comprehensive development tools from various FPGA vendors. After the synthesis, the comprehensive results of the simulation check are consistent with the original design. In the simulation, the integrated generated standard delay file is back-labeled into the comprehensive simulation model to estimate the impact of the gate delay. However, this step cannot estimate the line delay, so there is still a certain gap between the actual situation after the wiring and it is not very accurate. The current comprehensive tools are relatively mature. This step can be omitted for general design. However, if the circuit structure and design intent are found to be inconsistent after the place and route, it is necessary to go back to the integrated simulation to confirm the problem. Software tools introduced in functional simulation generally support post-synthesis simulation. Figure 4-1 Typical FPGA design flow Layout and routing can be understood as the use of implementation tools to map logic to the resources of the target device structure, determine the optimal layout of the logic, select the logic and the routing channels linked to the input and output functions to connect, and generate the corresponding files (such as configuration files and related Report), the implementation is to configure the integrated generated logic netlist to a specific FPGA chip, layout and routing is the most important process. The layout logically configures the hardware primitives and underlying elements in the logical netlist into the intrinsic hardware architecture inside the chip, and often requires a choice between optimal speed and optimal area. According to the topology of the layout, the wiring utilizes various connection resources inside the chip to reasonably and correctly connect the components. At present, the structure of the FPGA is very complicated, especially when there are timing constraints, the timing-driven engine needs to be used for layout and routing. Once the cabling is complete, the software tool automatically generates a report that provides information on the use of various parts of the design. Since only the FPGA chip manufacturer knows the chip structure best, the layout and wiring must choose the tools provided by the chip developer. Timing simulation, also known as post-simulation, means that the delay information of the place and route is back-labeled into the design netlist to detect the presence or absence of timing violations (ie, timing constraints or device-specific timing rules are not met, such as setup time, hold Time, etc.) phenomenon. Timing simulation includes the most complete and accurate delay information, which can better reflect the actual working condition of the chip. Since the internal delays of different chips are different, different layout schemes also have different effects on the delay. Therefore, after place and route, it is necessary to analyze the timing relationship of the system and each module, estimate the timing relationship, estimate the system performance, and check and eliminate the competitive risk. Software tools introduced in functional simulation generally support post-synthesis simulation. Board level simulation is mainly used in high-speed circuit design. It analyzes the signal integrity and electromagnetic interference of high-speed systems, and generally uses third-party tools for simulation and verification. The final step in the design is chip programming and debugging. Chip programming refers to the generation of the used data file (bitstream stream file, Bitstream GeneraTIon), and then download the programming data to the FPGA chip. Among them, chip programming needs to meet certain conditions, such as programming voltage, programming timing and programming algorithms. Logic Analyzer (LA) is the main debugging tool for FPGA design, but it needs to bring out a large number of test pins, and LA is expensive. At present, mainstream FPGA chip manufacturers provide embedded online logic analyzers (such as ChipScope in Xilinx ISE, SignalTapII in Altera Quartus II, and SignalProb) to solve the above contradictions. They only need to occupy a small amount of logic resources of the chip. High practical value. Gas Explosion-Proof Motor,Explosion Proof Motors,Gas Explosion Proof Motors,Explosion Proof Electric Motor Yizheng Beide Material Co., Ltd. , https://www.beidevendor.com