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In recent years, as the clock frequencies of microprocessors, DSPs, and digital ASICs have increased, the data rate and bus throughput of backplane signals have also steadily increased in some emerging fields. The increase in speed makes the weakness of single-ended signals based on TTL more and more prominent, mainly manifested in: increased power consumption, jitter (leading to bit errors), high-level radiation, etc., although some reports believe that the rate can be maintained at Above 50MHz, however, due to transmission line impedance mismatch and crosstalk, as well as more difficult power supply decoupling issues, designers are forced to seek more effective solutions.
One way to increase the bandwidth of all buses and backplanes is to increase the width of the bus, but this method will increase the difficulty of the layout of the circuit board, and requires a connector with a large number of pins, resulting in increased system cost and is very cumbersome. When the distance exceeds a few centimeters, serial communication is an effective solution to the above problem. High-speed communication systems, such as 3G base stations, routers, load / unload multiplexers, and other devices, can benefit greatly from serial communication.
In order to ensure that the backplane communication has low bit error rate, low crosstalk and low radiation, it is recommended to replace the TTL signal with a low voltage differential signal (LVDS). The characteristics of LVDS, ECL, PECL, and CML LVDS has become more and more widely used in systems that require signal integrity, low jitter (jitter is defined as the deviation of the signal's output transition time from the ideal value), and higher common model characteristics. application. It is one of the effective schemes currently used for high-speed serial interfaces. Other standards include (from low to high speed arrangement): ECL (emitter coupled logic), PECL (positive ECL), CML (current mode logic), each standard is different from each other.
ECL is a traditional high-speed logic standard. It is based on a bipolar crystal differential pair and uses a negative bias power supply. PECL is developed from the ECL standard, which eliminates the negative power supply in the PECL circuit. The new generation of ECL devices have a delay time of about 200ps and can be applied to systems with frequencies greater than 3GHz.
Among the existing interface standards, CML has the highest working rate and can be used for gigabit data rate systems. Compared with other standards, it also has an integrated 50Ω matching resistor, which greatly simplifies the design. When each endpoint works at a different power supply voltage, an external coupling element is required.
This article mainly discusses the characteristics of LVDS and its possible applications. Table 1 lists the characteristics of LVDS relative to ECL, PECL, and CML systems. According to the EIA / TIA-644 LVDS and IEEE 1596.3 standards, LVDS uses differential signals with a signal range of 250mV To 400mV, DC bias 1.2V.
Table 1. The swing of the output signal of the ECL and PECL transmitter is higher than that of the LVDS. The higher output swing and shorter transmission delay make the ECL and PECL devices have higher cost and power consumption.
The advantage of LVDS's differential characteristics brings many advantages to LVDS: it suppresses common mode noise and does not generate noise itself (assuming that the differential signal is fully synchronized and there is no distortion between the positive and negative outputs). In addition, LVDS can be implemented in a CMOS process to facilitate integration with other circuits. DifferenTIal Voltage Swing DC Offset PropagaTIon Delay
Because LVDS is a differential signal, the peak value of the current drawn by the power supply is low, and only a suitable decoupling capacitor can be added to solve the problem of power supply decoupling. Usually LVDS consumes less power than ECL and CML. Of course, it depends to some extent on the matching scheme used. Application of LVDS LVDS is mostly used for clock distribution and signal distribution from one point to many points. Clock distribution is very important for digital systems that require the same reference clock for different subsystems. For example, in most cases, the DSP of the base station needs to be synchronized with the RF signal processor, and the phase-locked loop (PLL) is used to generate the required LO frequency. The conversion is latched to the center reference clock. When working with a wireless receiver, the clock must also be distributed with the lowest possible radiation to avoid impact on the small signal path.
Different strategies can be used when distributing high-speed signals to different units. There are two extreme cases: one is to distribute the signal of one signal source / driver to all units (called "multipoint distributor"); the other The multi-channel signal is distributed to a unit (called "multipoint to single point distributor". Figure 1 illustrates the difference between the two cases. For a multipoint distributor, the driver must ensure that it can drive all receivers and transmissions. Medium (cable, connector, backplane), the bus usually needs to add matching impedance at the final receiver. The distance between all branches and the bus must be as short as possible to avoid causing signal integrity problems. Density circuit boards are not easy. 
Figure 1. Multipoint signal distribution allows communication between a transmitter and multiple receivers without the need for an intermediate connector and also eliminates interference caused by the connector.
Multi-point to single-point distribution structure requires multiple drivers, which can be defined as point-to-point operation, which is equivalent to the communication between the driver and a local terminal receiver. This structure reduces signal integrity issues, ensures that the impedance of the transmission medium is as consistent as possible, and eliminates interference caused by multiple branches.
Abstract: Compared with ECL, PECL and CML standards, ANSI EIA / TAI-644's Low Voltage Differential Signaling (LVDS) standard has the advantages of low power consumption and low noise radiation. This article mainly discusses the characteristics of LVDS and its possible applications.