One.... Try not to use judgment statements such as "greater than" and "less than", which will significantly increase the number of logical units used. Look at the report, the resource usage is very different. 5V 2.4A Usb Charger,5V2.4A Adapter Usb Charger,Ul Usb Wall Charger,Ul 60950 Usb Wall Charger Guangdong Mingxin Power Technologies Co.,Ltd. , https://www.mxpowersupply.com
Routine: always@(posedge clk) begin count1=count1+1; if(count1==10000000) feng=1; //no_ring else if(count1==90000000) begin feng=0; //ring count1=0; Endend //This will use 107 logical units
// If you change this sentence if(count1==10000000) to be greater than or less than 135 logical units in the report.....be sure to try to reduce the length of the reg register last time [30:0 ] Changed to [50:0], the logic unit in the report went from more than 100 to more than 2,000! It was too scary, as for why I didn't know it!
Three....case statement must be added to the default if you must add else
If it is the design of combinatorial logic, without default or else, there is no guarantee that all cases will be assigned, and a latch will be formed inside. It is no longer a pure combinatorial logic, and the circuit performance will drop.
For example: case({a,b})
2'b11 e=b;
2'b10 e=a;
Endcase
//Do not add default, although only care about the result of a=1, but when a=0, e will save the original value until a becomes 1
/ / Then e to save the original value, it is necessary to generate a latch inside.
4.. Try to use the Case statement instead of the if--else statement. Complex if--else statements usually generate priority decoding logic, which will increase the combined delay on these paths to generate complex logic. Statements usually generate parallel logic five without too much delay... In the always block of combinatorial logic, be aware that all inputs are placed in sensitive variable tables such as: always@(a or b)
Begin
Out=(a&b&c);
End
What is generated at this time is not pure combinatorial logic, because when C changes, out does not change immediately (you need to wait until a or b changes, c changes will appear), so you need to generate a register to hold the value of C.
Synthesis of consecutive assignment statements: extract logic from the right side of the assignment statement to drive the net to the left of the assignment statement
Synthesis of a procedure assignment statement: The logic extracted from the right side of the assignment statement is used to drive the reg variable to the left of the assignment statement. Note: The iniTIa statement is only used for simulation and is not integrated. Can only be integrated in always.
It is recommended that the combinatorial logic use blocking statements, the sequential logic uses non-blocking statements, and any delay control (such as #5) is ignored by the synthesis tool. The same variable in a module cannot have both blocking and non-blocking assignments.
The synthesis of the always statement
1 For combinatorial logic, the event list must include the variables referenced in all the always statements, otherwise the combined results will not match the design features.
2 Temporary variables can be omitted from the list of events.
The synthesis of the if statement In particular, pay attention to the synthesis of the latch. Always, a variable is not assigned in all conditional branches, and the latch is synthesized.
Case statement synthesis Like the if statement, incomplete case branch statements can also cause latch synthesis.
Ways to avoid:
1) Before the case statement, assign the initial value to the variable to be assigned
Always @ (state or a or b) begin
q =0;
Case(state)
3'b000: q = A & B;
......
2) Use the default branch statement
3) Use the integrated instruction, the specific usage inserts "synthesis full_case" in the comment of the case keyword line.
Parallel CASE Statement Normally, the case statement and the if statement will be combined with the hardware circuit with priority decoding, and the priority of the upper hero option is gradually reduced. But if the designer knows that all items in the case statement are mutually exclusive, then use the "parallel_case" synthesis directive.
Always @(key)
Case(key) //synthesis parallel_case
4'b0001: a = 0;
Endcase