This article refers to the address: http:// Abstract: This paper introduces the interface implementation method of audio decoding chip CS43L42 and embedded processor EP7212 produced by CIRRUS LOGIC. The MP3 file playback system based on embedded processor EP7212/7312 and CS43L42 chip is analyzed. Complete hardware connection diagram and effective software implementation. Keywords: embedded processor; digital audio interface DAI; CS43L42; MP3; EP7212 1 Introduction Currently, audio data formats for storing sound information mainly include PCM files, VOC files, MIDI files, MP3 files, and the like. For the navigation system, to achieve audio file playback, memory capacity is a problem to consider. Due to the limited storage space of the navigation system, the file compression required is high. Compared with other file formats, MP3 audio files have higher compression ratio and are inferior to CD sound quality, so the audio file storage in the navigation system uses MP3 format. The full name of MP3 is MPEG1 Layer-3 audio file, and MPEG? Moving Picture Experts Group? is translated into Chinese as the active image expert group, especially the active video compression standard. MPEG audio file is the sound part of MPEG1 standard, also called MPEG audio layer. It is divided into three layers according to compression quality and coding complexity, namely Layer1, Layer2 and Layer3, corresponding to three sound files of MP1, MP2 and MP3. Different levels of coding are used depending on the purpose. The higher the level of MPEG audio coding, the more complex the encoder and the higher the compression ratio. The compression ratios of MP1 and MP2 are 4:1 and 6:1 to 8:1, respectively, while the compression ratio of MP3 is as high as 10:1~ 12:1, that is to say, one minute CD quality music, 10MB of storage space without compression, and only about 1MB after MP3 compression encoding. However, MP3 uses a lossy compression method for audio signals. In order to reduce the sound distortion, MP3 adopts “sensory coding technologyâ€, that is, the spectrum analysis of the audio file is performed first, and then the filter is used to filter out the noise level. Then, each of the remaining bits is rearranged by quantization, and finally an MP3 file having a higher compression ratio is formed, so that the compressed file can achieve a sound effect closer to the original sound source during playback. The CS43L42 is an audio decoder chip produced by CIRRUS LOGIC. The CS43L42 has a DAI interface that works well with the embedded processor EP7212/7312. It has three modes: two-wire mode, SPI mode, and STAND ALONE mode. These three modes can be set by setting the corresponding status to the pins CP/SA and AD0/CS/DEM0. When the CP/SA pin is low, the chip is in STAND ALONE mode. When CP/SA is high, it will enter SPI mode whenever it detects that the pin AD0/CS/DEM0 level changes from low to high. It is a two-wire mode. In STAND ALONE mode, the SCL/CCLK/DIF1 and SDA/CDIN/DIF0 pins can be used to set the relationship between data, left/right clock, and master clock. In 2-Wire mode and SPI mode, you can perform functions such as mute, channel attenuation, and volume control by operating the registers. Figure 1 is the internal schematic diagram of the CS43L42, and Figure 2 is a schematic diagram of the pin arrangement of the chip. The functions of each pin are as follows: 1 pin (RST): Reset signal, active low. 2 feet (LRCK): Left/Right frame synchronization. 3 feet (SDATA): Serial audio data, data is introduced with the serial clock. Pin 4 (AD0/CS/DEM0): Used to enable the control port in SPI mode. Pin 5 (SCLK/DEM1): Bit clock, equal to 1/2 of MCLK, 128 bits per frame. 6-pin (VL): Digital supply voltage, typically 1.8V to 3.3V. 7-pin (MCLK): 2x oversampling clock, input only in slave mode. 9-pin (SDA/CDIN/DIF0): Serial control data input and output. 10 feet (N.C.): no connection, hanging. 11-pin (CP/SA): Control mode and standby mode control. 12 feet (VQ_HP): Headphone static voltage interface. Pin 13 (REF_GND): Connect to analog ground. 14-pin (FILT+): Forward reference voltage for internal sampling circuitry. 15 feet (VQ_LINE): Line output static voltage interface. 16? 21 feet (HP_A, HP_B): headphone output. Pin 17 (GND): Connect to analog ground. 18-pin (VA): Analog supply voltage, typically 1.8V to 3.3V. 19 feet (VA_LINE): linear amplifier power supply terminal, typical value is 1.8V ~ 3.3V. 20 feet (VA_HP): Headphone amplifier power supply terminal, typical value is 0.9V ~ 3.3V. 22, 23 feet (AOUTB? AOUTA): Analog output. 24 feet (MUTEC): mute control. If the chip in the system works in the STAND_ALONE mode, set DIF1 and DIF0 to low and high respectively to receive the valid 24-bit data from the left. Figure 3 shows a typical peripheral connection circuit for the CS43L42. The capacitance C in the figure is given by: C=(RL+560)/[4Ï€ Fs(RL·560)] 4 MP3 player software design The software design tasks for MP3 file playback are as follows: (1) Initialize the DAI interface of the EP7212. (2) Decode the MP3 file into a PCM file and store it in two buffers (left and right channels). (3) Write data in PCM format to the DAI interface in FIQ (Quick Interrupt Request) and play the sound at the same time (play mute when there is no data). 4.1 Introduction and initialization of the DAI interface of EP7212 a. DAI interface The Digital Audio Interface (DAI) of the EP7212/7312 is primarily used to support high quality stereo audio processing. Figure 4 shows the DAI interface circuit of the CS43L42 and the embedded microprocessor EP7212. The interface consists of the following five signals: (1) LRCK, left/right frame synchronization. (2) SCLK, bit clock, equal to 1/2 of MCLK, 128 bits per frame. (3) MCLK, 2x oversampling clock, input only in slave mode. (4) SDOUT, digital audio data output. (5) SDIN, digital audio data input. Adjusting the format with MSB/Left data means that the data is clocked immediately after the frame sync signal (LRCK) potential is changed. The MSB is left-adjusted in the first place, which is somewhat different from the I2S format. The data in the I2S format is delayed by one clock after changing the potential. The data frame is 128 bits long per frame, so each channel is 64 bits long. The frame size and the LRCK run cycle cannot be set in EP7212/7312. SCLK is available from MCLK with a frequency equal to 1/2 MCLK. In the default mode, DAI is in master mode. The MCLK clock generated by this mode is equal to 9.216MHz. Thus, SCLK is equal to 4.608MHz. For applications that require different rates of SCLK, the DAI can be set to slave mode. In slave mode, the external source supplies the master clock to MCLK through the MCLK pin, and then splits into two halves to generate SCLK. Regardless of how the DAI mode is set, SCLK and LRCK are usually set to output. Data is typically latched on the rising edge of SCLK and released on the falling edge. The DAI interface is a high quality digital audio interface that can be connected to audio devices that are compatible with the DAI interface. The DAI interface of the EP7212 generates 128-bit frame data using a bit clock and a frame-synchronous clock. Both digital audio data is received and transmitted in full-duplex mode, corresponding to a receive FIFO of 12 samples deep and a transmit FIFO of 8 sample depth. In the DAI interface signal, MCLK is the main clock, which is 256 times the audio sampling frequency, SCLK is 128 times the audio sampling frequency, and LRCK is fixed to the sampling frequency. Since the MCLK in this system is connected to an external clock generator, the frequency is 11.2896 MHz? Therefore, the sampling frequency is 44.1 KHz. Its DAI interface timing diagram is shown in Figure 5. b. DAI interface initialization The DAI initialization program should first set the control register, then select the external clock to be active and generate an interrupt when the left transmit FIFO data is less than half. The status register overflow and underflow bits are then cleared, and then the DAI interface, transmit FIFO, and receive FIFO are asserted. Finally open the DAI interrupt. 4.2 Decoding of MP3 files ARM provides an ARM-based audio file decoding library that can efficiently decode songs in MP3 format while outputting 16-bit stereo PCM data. a. Decoding the structure defined by the library tSampleRate defines the sampling rate of the decoded data PCM Typedef enum tagSampleRate { SR 11 025kHz? SR 12kHz? SR 44 1kHz? SR 48kHz? SR 32kHz? SR Reserved } tSampleRate ? tMPEGStatus gives the MP3 function return status value. Typedef enum tagMPEGStatus { eNoErr? eNoSyncword? eCRCError? eBrokenFrame? eEndOfBitstream? eDataOverflow? } tMPEGStatus ? tMPEGBitstream? gives a pointer to the MPEG bitstream, bufptr is defined as the word pointer of the bitstream, and bitidx is defined as the index in the word (0-31). Typedef struct tagMPEGBitstream { Unsigned int * bufptr? Unsigned int bitidx? } tMPEGBitstream? tMPEGHeader? includes MPEG audio header information, sam-ple_rate is the PCM sampling frequency, samplesperchannel is the number of samples per channel, numchans is the number of channels, packed info is the header information, and bits required is the number of bits required for the next call to the function. Free format refers to the format of the bitstream. Typedef struct tagMPEGHeader { tSampleRate sample rate? Unsigned int samplesperchannel? Unsigned int numchans? Unsigned int packed info? Unsigned int bits required? Unsigned int free format? } tMPEGHeader? · InitMP3Audio?tMPEGInstance *inst? Function: Initialize the decoder to decode the pointer. MP3SearchForSyncword?tMPEGInstance *inst?tM-PEGBitstream *bs?length? Function: Find sync words in MPEG data. MP3DecodeInfo?tMPEGInstance * inst?tMPEGBit-stream * bs?tMPEGHeader * pmpeg hdr? Function: Get the information of the header from the MPEG frame. MP3DecodeData?tMPEGInstance *inst? short *left?short * right? tMPEGBitstream * bs? Function: Decode data from MP3 into PCM data and store it in the buffer pointed to by left and right. c. MP3 program decoding process and implementation in FIQ interrupt Figure 6 shows the decoding process of the MP3 file in the system. This file can be played in the FIQ interrupt. Since the DAI FIFO corresponds to the FIQ interrupt, it can set the interrupt mode of the FIFO through the control register, and can set the position where the interrupt is generated in the program to less than four samples of data in the left transmit FIFO. Since the address of the MP3 decoding buffer is stored in the FIQ interrupt, if four sample data are written to the left and right FIFOs after entering the FIQ, the FIQ rate will be 11 kHz for the 44.1 kHz file. In order to ensure the correct filling of the left and right FIFOs, it is generally necessary to alternately write two FIFOs. At this point, if there is no data in the MP3 buffer, you can write 0 (mute) to the two FIFOs, so that the program can jump out of the FIFO interrupt and then process the data. It should be noted that no matter whether the program needs recording or not, it must read four data from the receiving buffer, which ensures that the DAI FIFO is in sync without distortion. In addition, at the end of the FIQ handler, the overflow status bit is also cleared to prevent the FIQ from being interrupted at all times. High Voltage STA Armored Cable High Voltage STA Armored Cable is a type of Power Cable that is designed to carry high voltage electricity in a safe and efficient manner. It is commonly used in industrial and commercial applications where high voltage power is required for heavy machinery and equipment. PVC Sheathed Electric Cable,Copper Conductor Power Cable,High Voltage Xlpe Power Cable,High Voltage XLPE Insulated STA Armoured Power Cable,STA Armour High Voltage XLPE Cable Ruitian Cable CO.,LTD. , https://www.rtpowercable.com
   Although MP3 is a lossy compression method, it has a very small compression ratio for a higher compression ratio, so it can be applied in many occasions. Especially with the development of digital technology, MP3 compression has been widely used in portable electronic products, and is deeply loved by young and fashionable friends.
2 CS43L42 player chip It can work from 1.8 to 3.3V, and consumes only 16mW when turning off the linear amplifier. It is ideal for low-power applications such as MP3 and MD players. The chip is a complete digital-to-analog converter that includes 1-bit D/A conversion, analog filtering, volume control, linear voltage output, and headphone amplifier. By changing the main frequency, the allowed input sampling frequency can vary from 2k to 100kHz. The device features digital accents, peak limits, and de-emphasis. In addition, due to the use of POPGUARD technology, CS43L42 can also effectively prevent the instantaneous impact generated during power-on and power-off.
image 3
   Pin 8 (SCL/CCLK/DIF1): Serial control interface clock.
3 CS43L42 hardware connection circuit
Figure 5
   The frame length of the DAI is 128 bits. It includes an audio sample data. Of the 128 bits, only 32 bits are the actual audio data, and the rest of the output is zero. The left/right clock is used as the frame synchronization signal, and the left/right clock indicates the 16-bit data of the right channel from high to low, and the 16-bit data of the left channel from low to high.
   b. Functions provided by the MP3 decoding library
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