This article refers to the address: http:// 0 Introduction Nowadays, the high-speed development of voice signal processing technology has been widely used in the processing, transmission and storage of audio information. At the same time, with the increasing popularity of high-performance DSP, algorithm research and real-time implementation of voice signal processing using DSP is becoming new. Hot spot. Therefore, this paper designs and implements a speech acquisition and processing system, which aims to provide a general platform for algorithm research and real-time implementation of speech signal processing. 1 chip introduction TLV320AIC23 (hereinafter referred to as AIC23) is a high-performance Codec chip from TI. The main features are: built-in headphone output amplifier, support MIC and LINE IN two input modes (choose one), and have programmable gain adjustment for both input and output; A / D converter and D / A converter in the chip Multi-bit Sigma-Delta technology, data transmission word length is 16, 20, 24, 32bit, sampling rate is 8kHz ~ 96kHz; A/D converter signal-to-noise ratio reaches 90dB, D/A at sampling rate of 96kHz The converter reaches 100dB; the power in playback mode is 23mW, and in power-saving mode it is less than 15uW; it only takes up 25mm 2 area. Based on the above advantages, the AIC23 is ideal for applications such as analog digital audio playback and analog input and output for recording, such as MP3 players. TMS320VC5416 (hereinafter referred to as VC5416) is a 16-bit fixed-point high-performance DSP from TI, which is the third-generation chip in the TMS320VC54x series. The main features are: speed up to 160MI / s; three 16bit data memory bus and one program memory bus; one 40bit barrel shifter and two 40bit accumulators; one 17 × 17 multiplier and one 40bit Dedicated adder; maximum 8M × 16bit extended addressing space, built-in 128k × 16bit RAM and 16k × 16bit ROM; 3 multi-channel buffer serial port (McBSP); equipped with PCM3002, can perform voice A/D and D /A conversion. Due to its low power consumption and high performance, the VC5416's separate data and instruction space allows the chip to have a high degree of parallelism, allowing simultaneous access of instructions and data in a single cycle, coupled with a highly optimized instruction set. With high computational speed and the chip itself with rich on-chip memory resources and a variety of on-chip peripherals, it is widely used in the engineering community, especially in speech coding and communication applications. 2 system hardware structure 2.1 system hardware structure The voice acquisition and processing system mainly includes three main parts: a data processing module with VC5416 as the core; a voice acquisition and codec (CODEC) module with AIC23 as the core; and a memory module extended by users according to needs. The system hardware structure is shown in Figure 1. Figure 1 system hardware structure 2.1.1 Digital Signal Processing Chip In order to meet the real-time requirements of voice signal processing, the voice signal acquisition and processing system should have high-speed data processing capabilities. This system uses TMS320VC5416 chip as the signal processing chip. 2.1.2 Audio CODEC Module The CODEC module of this system is based on the TLV320AIC23 chip. 2.1.3 Power Module The VC5416 is a low-power fixed-point chip that operates from dual power supplies. The power supply consists of a core power supply (CVdd) and an I/O power supply (DVdd). The core power supply is 1.8V and the I/O power supply is 3.3V. The core power supply uses 1.8V to reduce power consumption; the I/O supply uses 3.3V to allow the chip to interface directly with external low-voltage devices without the need for additional level shifting circuitry. This system uses TI's TPS73HD318 (referred to as HD318) as the power input chip. The two output voltages provided by HD318 are 1.8V and 3.3V. In addition, the chip provides a low-level reset pulse with a width of 200ms, which can also be used as a power-on reset signal for the VC5416. The AIC23 chip has two power modes (single power supply (5V power supply) and dual power supply (3V digital power supply + 5V analog power supply). The system selects dual power supply mode, so that AIC23 and VC5416 can be directly connected without other levels. Conversion chip. 2.1.4 JTAG emulation interface The system is connected to the computer by the hardware emulator XDS510/PP through the JTAG emulation interface. The user can load the program to the VC5416 chip through this interface and observe the data of the internal memory of the chip to complete the tasks of system simulation and program debugging. If the system needs to work offline, you can use the JTAG emulation interface to burn the user program into the Flash Rom, and then set the boot mode pin to determine that the system boots from the off-chip ROM. 2.2 hardware interface design The VC5416 has three McBSPs, which can conveniently use two of the McBSPs to complete the control and communication of the AIC23. The McBSP0 of the VC5416 is connected to the data port of the AIC23, and the McBSP1 is connected to the control port of the AIC23. The AIC23 chip is a programmable chip with 11 16-bit registers inside. The control interface has SPI and I 2 C operation modes. These two modes of operation are selected by the MODE pin, ie: MODE=0 is I 2 C mode; MODE=1 is the SPI mode. The interface circuit of AIC23 and VC5416 is shown in Figure 2. Figure 2 AIC23 and VC5416 interface circuit The VC5416's two multi-channel buffer serial ports McBSP are configured in I 2 C mode and SPI mode respectively. McBSP0 acts as the transmit and receive port for the data; McBSP1 writes the control word to the CODEC as the control port; AIC23 acts as the slave, so it is set to Slave mode, while VC5416 is set to Master mode, and the Codec sample rate is set to 8 kHz. 2.3 BOOTLOADER design There is a solid self-loading program (BOOTLOADER) in the VC5416 on-chip ROM, but it has a limit on the size of the loaded program. In the case of using 8-bit Flash, only content smaller than 16KWord can be loaded. The total data volume of the program area and data area of ​​the three-rate SELP algorithm far exceeds 16KWord. Obviously, using only the on-chip BOOTLOADER is not enough. So you must write the loader yourself. First, the load program written by the VC5416 on-chip BOOTLOADER is loaded into the on-chip RAM, and then the loader is executed to load other parts. One of the main problems that need to be solved here is the mapping relationship between Flash data and on-chip address space. Since the total program data of the SELP algorithm is large, it is necessary to use an on-chip extended program area, that is, the MP/MC flag bit needs to be set to zero. From the Memory Map at this time, it can be seen that the VC5416 can access only 32K of each off-chip address space, so the Flash data can only be mapped to the on-chip address space according to the 32K per page. Using FPGA can easily control which page of Flash data is mapped into the chip. The block diagram of this part is shown in Figure 3. Figure 3 BOOTLOADER principle 3 interface software design The software of this system is written in a mixture of C language and assembly language. Since the McCSP port of the VC5416 is used to control the AIC23 chip, and the two McBSP ports are set to different working modes, the McBSP must be initialized to conform to the control command timing of the AIC23 chip and the required operation mode. Because this article only lists some of the code when initializing the VC5416 and AIC23 chips. 3.1 TMS320VC5416 initialization SWWSR=0x7fff; / program, data, I / O space SWCR=0x0001; /waiting period is 7×2=14 BSCR=0x8006;/By 32KW partition, HD[7:0], D[15:0]Hold CLKMD=PLL_DIV_INIT; Waitloop(0x0400); CLKMD=PLL_LOCK_INIT_X(5); Waitloop(0x0400); PMST=0x0168; / interrupt vector table is located at 0X100, MP/MC=1 OVLY=1, DROM=1; 3.2 TLV320AIC23 initialization In order for the AIC23 to function properly and produce the desired audio effects, its corresponding registers must be configured. First, the I 2 C VC5416 module initialization, a write address on the bus slave address register AIC23 ICSAR; AIC23 then the corresponding address mapping registers and internal write data to be combined into 16bit control word is written sequentially ICDXR, and The initial configuration of the AIC 23 can be completed by sending it to the AIC 23 via the I 2 C bus. Part of the source code for AIC23 initialization: Unsigned int codec_buf[9]={OX1e00, OXOc00, OxO81a, OxOaO4, OxOe01, 0x1020, 0x1021, 0x0117, OxO5f9}; Port_sub_address=(unsigned int*)MCBSP_SPSA_ADDR(1); Port_sub_index_reg=(unsigned int*)MCBSP_SPAD_ADDR(1); *Port_sub_address=MCBSP_SPCR2_SUBADDR; For(i=O;i<9;i++){ While(!(*Port_sub_index_reg&(MASK_BIT(XRDY))))); Set_codec_cs_low(); MCBSP1_DXR1=codec_buf[i]; While(!(*Port_sub_index_reg&(MASK_BIT(XRDY))))); Set_codec_cs_high();} 4 Conclusion The innovation of this paper is to design and implement a voice acquisition and processing system based on the characteristics of TI's DSP chip TMS320VC5416 and voice CODEC chip TLV320AIC23. The system has strong processing power and flexible peripheral buckle circuit. It has been proved that it can meet the requirements of real-time signal processing, and can be used as a general platform for speech signal processing algorithm research and real-time implementation. references: [1] Zhang Xiongwei, Cao Tieyong. The principle and development of DSP chip (Second Edition) [M]. Beijing: Publishing House of Electronics Industry, 2OO0 [2] Ren Lixiang, Ma Shufen, Li Fanghui. Principle and application of TMS220600 series DSP [M]. Beijing: Publishing House of Electronics Industry, 2OOO [3]DAI Mingxi, ZHOU Jianjiang. Structure, principle and application of TMS320VC54x DSP [M]. Beijing: Beijing University of Aeronautics and Astronautics Press, 2001 [4]TMS320VC5416 Bootloader.SPRA602C.Texas Instrument, February 2001 [5] TMS320VC5416 Fixed-Point Digital Signal Processor Data Manual.TI Corporation, 2003 [6] Stereo Audio CODEC, 8kHz-96kHz, with Integrated Head Phone Amplifier TLV320AIC23.TI Corporation, 2001 [7]Hao Soft, Xu Jinwei. Algorithm Implementation of MELP Vocoder Based on DSP Chip[J].Microcomputer Information,2006,10-2:62-64
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Keywords: data acquisition; DSP; TLV320AIC23; TMS320VC5416