After using ISE for more than half a month, almost all of them are self-taught. I have encountered many small problems that have made DT a long time. Baidu is also less than 100 years old. Later, it was solved. In order to make it easy to learn ISE children's shoes in the future. No longer entangled with some small problems, summed up the experience of these days. Ok, don't talk nonsense, feed! 1. When using ISE simulation, the variables used must be initialized. The default initial value of ISE is "XXXXX", and the default is "00000". In fact, the default is 0 after the FPGA, but it can be Say ISE is rigorous and DT. For example, with an accumulator, result = A+B+result, you must ensure that when A, B, and result are fixed at a certain moment, the subsequent data will not always be "XXXXX"; 2. All the middle lines (that is, the signals used to pass parameters between modules) must be defined by wire. This is generally reminded; 3. Any warning is useful; 4.debug should set the intermediate variable to output, and then view the simulation waveform; 5. In fact, the new version is still relatively easy to use. Although the test bench wave function is cancelled. But it is better to learn to test the file, later than the test bench wave, and it seems that once the test signal is too much, the test bench wave does not display. Some output; 6. warning: Nod <....> is unconnected. Indicates that the module where <...> is not used is executed. Generally, the parameter is not coming in, or the incoming parameter is not correct ("XXXX" or the like). . 7. When creating a rom, Error: sinrom can't be resolved. Because the sinrom.ngc file is not copied together when the program is moved. 8. One way to dispose of the "XXXXX" signal can be: Randomly select a if (data[0] == 0) ....; else if (data[0] == 1) from the signal. ... else data = 0; It is possible to clear the "XXXX" signal to "0000". It can solve the problem of simulation in 1 well. 9. If a signal that is not a clock is used as a periodic signal, then WARNING: Route: 455 - CLK Net: trn_clk_OBUF may have excessive skew. because 0 CLK pins and 1 NON_CLK pins failed to route using a CLK Template no matter what. 10. Don't be afraid when using FPGA at first, use ucf file to match the pin, directly LOAD, first do not need to control any area constraints, and then learn again. 11. Remember these for the time being, and add it later. Regular GFCI Receptacle Outlet Gfci Protected Outlet,Ground Fault Outlet,Grounding Outlets,Ground Fault Circuit Interrupter Outlet Lishui Trimone Electrical Technology Co., Ltd , https://www.3gracegfci.com