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The high-precision time-interval measurement chip TDC-GP1 developed by ACAM in Germany can provide two channels of 250ps or single channel 125ps resolution time interval measurement; users can easily use it to form their own system or instrument, so it has been used in many High-precision testing has been applied (such as high-precision laser range finder, frequency and phase signal analysis, etc.). The article details the internal structure of the TDC-GP1. The working principle and performance indicators, and an application example of the chip in measuring the delay time of the gate circuit.

1 Overview

TDC-GP1 is mainly used in ultrasonic flowmeter, high-energy physics and nuclear physics, high-precision laser range finder, laser radar, laser scanner, CDMA wireless cellular system wireless positioning, ultrasonic density meter for various handheld/airborne or fixed workers. High-precision testing fields such as ultrasonic thickness gauges, turbocharger speed testers, tensiometers, magnetostrictive sensors, time-of-flight spectrometers, astronomical time interval observations, frequency and phase signal analysis. The TDC-GP1 also provides a variety of interfaces to the microprocessor, making it easy for users to use it to build their own systems or instruments.

2 structure principle and pin function

The TDC-GP1 is available in a 44-pin TQFP package and features four main functional blocks: a TDC measurement unit, a 16-bit arithmetic logic unit, an RLC measurement unit, and an interface unit with an 8-bit processor. The internal structure is shown in Figure 1.

(1) TDC measurement unit

When the time difference between the rising or falling of two pulses is tens to hundreds of ns, the conventional pulse counting method for measuring the pulse width is no longer applicable. This is because the narrower the pulse to be measured, the higher the required clock frequency and the higher the performance requirements of the chip. For example, when a measurement error of 1 ns is required, the clock frequency needs to be increased to 1 GHz. At this time, the general counter chip is difficult to work normally, and also causes problems such as wiring, material selection, and processing of the board. In order to overcome the above problems, TDC-GP1 uses a signal to pass the absolute transmission time of the logic gate circuit to propose a new time interval measurement method. The measurement principle is shown in Figure 2. The time interval between the START signal and the STOP signal is determined by the number of non-gates, and the transmission time of the non-gate can be accurately determined by the integrated circuit process. At the same time, since the transmission time of the gate circuit is greatly affected by the temperature and the power supply voltage, the phase lock and calibration circuit are designed inside the chip.

(2) 16-bit arithmetic logic unit

As shown in Figure 1, the TDC-GP1 has two arithmetic logic units (ALUs). The previous ALU converts the measurement in the coarse register into an unsigned integer for subsequent ALU arithmetic operations. The following 16-bit sequential ALU mainly performs the following three aspects: calculating the time interval according to the instruction in the control register; calibrating the calculated result; and multiplying the calibrated result. The ALU has an independent clock that takes only 4μs to complete all of the above.

(3) RLC measuring unit

The TDC-GP1 integrates an RLC measurement unit on the chip using its own time interval measurement function. First, a known capacitor is discharged through the measured resistance. When the discharge voltage on the capacitor reaches the threshold voltage of the comparator, the TDC-GP1 records the discharge time. Then, the measured resistance is converted into a resistor of a known resistance, and the above process is repeated to obtain another discharge time. According to the ratio of the two discharge times and the resistance of the known resistance, the resistance of the measured resistance can be calculated.

(4) Interface unit with the microcontroller

TDC-GP1 provides an interface to an 8-bit microcontroller, including an 8-bit data bus, 4-bit address lines for 16 register operations, and control lines such as read, write, and chip select. In addition, to simplify the interface design, an address latch line (ALE) is also provided.

3 Functional Description

The TDC-GP1 offers three modes, two ranges and adjustable accuracy, which can be selected by the user. The resolution in each mode can be set to high or low. The following is a brief introduction to the test process and timing of the three modes.

(1) Range 1

The TDC-GP1 provides two measurement channels, each with 250 ps accuracy, and the two channels have the same accuracy level; the two channels share an STSRT input that can be compared to four independent STOP inputs with a minimum time limit of 15 ns; START The STOP signal must last for more than 2.5 ns, otherwise the chip cannot be recognized; the STOP signals can be compared with each other without a minimum time limit; the range is 3 ns to 7.6 μs; the two channels can be sorted, so that 8 channels can be allowed for 1 channel. Pulse input, the STOP input of channel 2 is ignored in this mode. Figure 3 shows the measurement timing for range 1.

(2) Range 2

For large-scale time measurements, the chip introduces a 16-bit predivider. In this mode, only the channel 1 is available for the chip; four pulse inputs are allowed in the normal accuracy mode; the STOP signals cannot be compared with each other, and only the STOP and STSRT signals can be compared; the maximum range is 60 ns to 200 ms. Figure 4 shows the measurement timing for range 2.

The principle is as follows: input the START signal, the chip internally quickly measures the time difference between this signal and the next calibration clock rise, recorded as tFC1. After that, the counter starts working and gets the number of work cycles of this predivider, which is recorded as period. In this case, the internal measurement unit of the chip is reactivated, and the time difference between the rising edge of the first pulse of the input STOP signal and the rising edge of the next calibration clock is measured, and is recorded as tFC2. TFC3 is the time difference between the rising edge of the second pulse of the STOP signal and the rising edge of the calibration clock, tCall is a calibration clock cycle, and tCal2 is two calibration clock cycles. According to FIG. 4, the time interval between the START signal and the first pulse of the STOP signal is time=period×[CC+(tFC1-tPC2)/(tCal2-tCal1)cc represents the count value of the predivider.

(3) Precision adjustable mode

Another important feature of the TDC chip is that the device introduces an accuracy adjustment mode. In this mode, the two channel values ​​are very accurate. The calibration loop routes the external clock introduction as a reference. We can work in this mode by setting the internal registers of the chip, so the accuracy of the results depends on the settings in the program. Accuracy adjustable mode does not require a START signal, so a maximum of 8 STOP inputs can be introduced through Channel 1 and Channel 2. At this time, any two STOP signals can be compared, and the range is 3 ns to 3.8 μs. Working in the precision adjustable mode, the chip consumes a relatively large amount of power, about 25mA. Figure 5 shows the test sequence for the precision adjustable mode.

4 application examples

The delay time of a high-speed logic gate circuit is generally only a few ns, which cannot be measured by the previous pulse counting method. This type of work becomes much easier with the TDC-GP1. Figure 6 is a measurement block diagram and timing diagram thereof, and Figure 7 is a specific circuit principle. The register of application range 1 is set to: Reg0:0x44;Reg1:0x4D;Reg2:0x01;Reg3:0xXX;Reg4:0xXX;Reg5:0xXX;Reg6:

0x02; Reg7: 0x01; Reg8: 0x00; Reg9: 0x00; Reg10: 0x80.

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